EN0-001 Online Practice Questions and Answers

In which type of storage will the compiler preferentially place frequently accessed variables?

A. Stack

B. Heap

C. Registers

D. Hard disk

An ARMv7 implementation might include the VFPv4-D32 floating point extension. What does the '32' indicate?

A. The width of the datapath in bits

B. The number of double precision floating point registers implemented

C. The number of bits of data that can be loaded or stored at once

D. The number of integer operations that can be performed simultaneously

In the ARM instruction set what is the maximum branch distance for a Branch or Branch and Link instruction?

A. ±32MB

B. ±4MB

C. ±12KB

D. ±4KB

Which one of the following debug methods is the least intrusive for analyzing a timing related bug?

A. Place breakpoints on strategic locations to locate the problem area

B. Instrument the code with print statements to locate the problem area

C. Use debug hardware to place watchpoints on strategic data memory locations

D. Use trace hardware to capture a trace log up to the point of the crash

In which TWO of the following locations would a compiler typically place local variables? (Choose two)

A. ROM

B. Heap

C. Cache

D. Registers

E. Stack

When linking with the standard C library, which library functions MUST be redefined in order to port your code to a new piece of production hardware?

A. Functions that are not compliant with the ISO C library standard

B. Functions that are not compliant with the 1985 IEEE 754 standard for binary floating-point arithmetic

C. Target-dependent functions which use semihosting

D. Functions called implicitly by the compiler

Under which of the following circumstances would a DSB instruction be used?

A. In a multi-threaded system, when two threads need to be synchronized at a particular point

B. When accessing a peripheral, it is necessary to halt until the memory access is complete

C. When it is necessary to temporarily disable interrupts while carrying out a particular memory access

D. In a multiprocessor system, when it is necessary to halt one of the cores while the other completes a critical task

Assuming a 4-core Cortex-A9 SMP system which does not use the Accelerator Coherency Port (ACP). and operates the L1 caches in writeback mode, in which of the following situations is a cache clean operation required?

A. An external DMA engine modifies data in a region of data memory which is already cached by the processor

B. An external agent needs to read data which has been modified by the processor in a cacheable memory region

C. Debugger reads data from a shared, cacheable memory location

D. One core modifies data in a shared cacheable memory region

The Performance Monitoring Unit (PMU) of a Cortex-A9 processor permits direct measurement of which one of the following?

A. Cache Size

B. Clock Speed

C. Program size

D. Numbers of instructions executed

If the performance of an application remains unchanged when the core clock speed of a Cortex-A9 processor is reduced, what can you deduce about the system?

A. The Clocks Per Instruction (CPI) of the processor has increased

B. The processor is NOT the limiting factor on performance

C. Instruction cache utilization has improved

D. The core has stopped carrying out speculative data memory accesses